---------------------------------------------------------------- -- Project : agfo10_a.ise -- 25042008-RRI-RAL-hydrus-KPA -- File : usb_agfo5.vhd -- The original source code copied from Kamini - 11022008 ---------------------------------------------------------------- ---------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; library UNISIM; use UNISIM.VComponents.all; entity usb_agfo5 is Port ( CLK : in std_logic; CLK2 : in std_logic; SCTN : in std_logic; RESET_IN : IN STD_LOGIC; U_WR_usb : IN STD_LOGIC; U_RD_usb : IN STD_LOGIC; U_ADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0); CHIP_SEL : IN STD_LOGIC_VECTOR(1 downto 0); U_DATA : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0); READ_REG : IN STD_LOGIC_VECTOR(31 DOWNTO 0); TO_USB_READ1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); TO_USB_READ2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); TO_USB_READ3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); TO_USB_READ4 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); TO_USB_READ5 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); tile0_refclkout_i_out : IN STD_LOGIC; tile1_refclkout_i_out : IN STD_LOGIC; TILE0_TXUSRCLK20_OUT : IN STD_LOGIC; TILE1_TXUSRCLK20_OUT : IN STD_LOGIC; tile0_rxclk0_i : IN STD_LOGIC; tile0_rxclk1_i : IN STD_LOGIC; tile1_rxclk0_i : IN STD_LOGIC; tile1_rxclk1_i : IN STD_LOGIC; mgtreset : IN STD_LOGIC; POL_SELECTION : OUT STD_LOGIC; PIPELINE_EN : OUT STD_LOGIC; OUTPUT_REG : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); WALSH_WREN_out : OUT STD_LOGIC; WALSH_OPREG_LOAD : OUT STD_LOGIC; FIBER_OPREG_LOAD : OUT STD_LOGIC; GAIN_WREN1_out : OUT STD_LOGIC; GAIN_WREN2_out : OUT STD_LOGIC; CHSEL_WREN_out : OUT STD_LOGIC; OPREG_LOAD_out : OUT STD_LOGIC; SER_WREN_out : OUT STD_LOGIC; SER_OPREG_LOAD : OUT STD_LOGIC; SCTN_WREN_out : OUT STD_LOGIC; SCTN_OPREG_LOAD : OUT STD_LOGIC; EXTRST_WR_EN : OUT STD_LOGIC; RST_OPREG_LOAD : OUT STD_LOGIC; OPREG_RDEN : OUT STD_LOGIC ); end usb_agfo5; ----------------------------------------------------------------- architecture behavioral of usb_agfo5 is --type ST_TYPE is (idle,pol_state, write,read); type ST_TYPE is (pol_state, write1,write2,write3,write4,write5,write6, read1,BURST_READ); signal STATE_RW: ST_TYPE ; --signal start_wr_action,start_rd_action : std_logic; signal U_WR_CNT,U_RD_CNT : std_logic_vector(7 downto 0); signal go_back_w: std_logic; signal reg_addrs : std_logic_vector( 4 downto 0); signal O_DATA_int1,O_DATA_int2 : std_logic_vector(7 downto 0); signal O_DATA_int3,O_DATA_int4 : std_logic_vector(7 downto 0); --signal go_to_idle_w,go_to_idle_r : std_logic; signal wr_en,rd_en,rd_en1 : std_logic; signal pipeline_sel : std_logic; signal O_DATA_REG : std_logic_vector( 31 downto 0); signal TO_FPGA,TO_USB,T : std_logic_vector(7 downto 0); signal L_UADDR : std_logic_vector( 7 downto 0); signal valid_WR,valid_RD : std_logic; signal wr_cnt, rd_cnt : std_logic; signal check_wr_low,check_rd_low,U_WR_int,U_RD_int: std_logic; signal U_WR,U_RD : std_logic; signal OPREG_WREN,WE_EN : std_logic; signal OPREG_LOAD : std_logic; signal loc_ctr : std_logic_vector(7 downto 0);--:=(others => '0'); signal ch_ctr : std_logic_vector(5 downto 0):=(others => '0'); signal inc_ch_ctr : std_logic; signal POL_SELECTION_INT : std_logic; signal inc_loc_ctr : std_logic; signal OP_WR_EN1,OP_WR_EN2 ,RESET, RESET_IN_int: std_logic; SIGNAL WALSH_OPREG_LOAD_INT,SER_OPREG_LOAD_INT,FIBER_OPREG_LOAD_INT,FIBER_WREN_out: STD_LOGIC; SIGNAL SCTN_OPREG_LOAD_INT,RST_OPREG_LOAD_INT,rst_loc_ctr,CHSEL_WREN_out_int,WR_ENABLE : STD_LOGIC; signal CHECKSUM : std_logic_vector(7 downto 0):=(others => '0'); signal CHECKSUM_OUT1,CHECKSUM_OUT2 : std_logic_vector(7 downto 0):=(others =>'0'); signal rst_uramloc_ctr,URAM_RD_LD,URAM_INC,URAM_RDEN : std_logic:='0'; signal uram_ctr : std_logic_vector(4 downto 0):=(others => '0'); signal renram1,READ_complete,Write_completel, READ_completel,RW_DONE,Write_complete: std_logic:='0'; signal SCTN_L,poll_next_sctn: std_logic:='0'; signal READ_status :std_logic_vector(31 downto 0); signal wr_addrs,rd_addrs : std_logic_VECTOR(4 downto 0):=(others => '0'); signal USB_READRAM_IP: std_logic_vector(31 downto 0); signal wea: std_logic_VECTOR(0 downto 0); signal COMMAND1_DATA,COMMAND2_DATA: std_logic_vector(31 downto 0); signal COMMAND3_DATA,COMMAND4_DATA: std_logic_vector(31 downto 0); signal COMMAND5_DATA,COMMAND6_DATA: std_logic_vector(31 downto 0); signal SCTN_COUNT,CLK_COUNT : std_logic_vector(31 downto 0):=(others => '0'); signal tile0refclk1_cnt,tile1refclk1_cnt: std_logic_vector(31 downto 0):=(others => '0'); signal tile0txclk_cnt,tile1txclk_cnt: std_logic_vector(31 downto 0):=(others => '0'); signal tile0rxclk0_cnt,tile0rxclk1_cnt: std_logic_vector(31 downto 0):=(others => '0'); signal tile1rxclk0_cnt,tile1rxclk1_cnt: std_logic_vector(31 downto 0):=(others => '0'); signal CLKCOUNT,SCTNCOUNT: std_logic_vector(31 downto 0):=(others => '0'); component usbreadram32 port ( clka: IN std_logic; dina: IN std_logic_VECTOR(31 downto 0); addra: IN std_logic_VECTOR(4 downto 0); ena: IN std_logic; wea: IN std_logic_VECTOR(0 downto 0); clkb: IN std_logic; addrb: IN std_logic_VECTOR(4 downto 0); enb: IN std_logic; doutb: OUT std_logic_VECTOR(31 downto 0)); end component; ----------------------------------------------------------------- begin U_WR <= NOT U_WR_usb; U_RD <= NOT U_RD_usb; usb_reset_cap:process(CLK,RESET) begin if CLK'event and CLK = '1' then RESET_IN_int <= RESET_IN; RESET <= RESET_IN_int; end if; end process; TRI_CONTROL: FOR i IN 0 TO 7 GENERATE T(i) <= not rd_en ; --rw_control; END GENERATE; IOBUF_inst1 : FOR i IN 0 TO 7 GENERATE iobuf1: IOBUF GENERIC MAP ( DRIVE => 12, IOSTANDARD => "LVCMOS33", SLEW => "SLOW") PORT MAP ( O => TO_FPGA(i), -- Buffer output IO => U_DATA(i), -- Buffer inout port (connect directly to top-level port) I => TO_USB(i), -- Buffer input T => T(i) -- 3-state enable input ); END GENERATE; ---------------------------------------------------------------------------------- reg_addrs <= L_UADDR(7 DOWNTO 3); --U_ADDR(6 DOWNTO 3); ---------------------------------------------------------------------------------- process(CLK,RESET,U_WR,U_RD) begin if CLK'event and CLK = '1' then if RESET = '1' then U_WR_int <= '0'; U_RD_int <= '0'; L_UADDR<= (others => '0'); wr_cnt <= '0'; valid_WR <= '0'; check_wr_low<= '0'; wr_cnt <= '0'; valid_WR <= '0'; check_rd_low<= '0'; else U_WR_int <= U_WR; U_RD_int <= U_RD; end if; if U_WR_int = '1' and check_wr_low = '0' then wr_cnt <= not wr_cnt; if wr_cnt = '1' then valid_WR <= '1'; check_wr_low <= '1'; L_UADDR<= U_ADDR; wr_cnt <= '0'; else L_UADDR<= L_UADDR; end if; elsif U_WR_int = '0' and check_wr_low = '1' then check_wr_low<= '0'; wr_cnt <= '0'; elsif U_WR_int = '0' and check_wr_low = '0' then valid_WR <= '0'; wr_cnt <= '0'; check_wr_low<= '0'; elsif U_WR_int = '1' and check_wr_low = '1' then valid_WR <= '0'; --valid_WR; wr_cnt <= '0'; --wr_cnt; check_wr_low<= check_wr_low; end if; if valid_WR = '1' then valid_WR <= '0'; end if; if U_RD_int = '1' and check_rd_low = '0' then rd_cnt <= not rd_cnt; if rd_cnt = '1' then valid_RD <= '0'; check_rd_low <= '1'; rd_cnt <= '0'; end if; elsif U_RD_int = '0' and check_rd_low = '1' then check_rd_low<= '0'; valid_RD <= '1'; elsif U_RD_int = '0' and check_rd_low = '0' then valid_RD <= '0'; rd_cnt <= '0'; check_rd_low<= '0'; elsif U_RD_int = '1' and check_rd_low = '1' then valid_RD <= valid_RD;--'0'; --valid_WR; rd_cnt <= '0'; --wr_cnt; check_rd_low<= check_rd_low; end if; if valid_RD = '1' then valid_RD <= '0'; end if; if valid_WR = '1' then if reg_addrs = "00000" then -- command word for esc seq go_back_w <= '1'; else go_back_w <= '0'; end if; end if; else go_back_w <= go_back_w ; U_WR_int <= U_WR_int; U_RD_int <= U_RD_int; L_UADDR <= L_UADDR; valid_WR <= valid_WR; valid_RD <= valid_RD; end if; end process; --write/read process state_logic:process (CLK,RESET,reg_addrs,go_back_w) begin if CLK'event and CLK='1' then if RESET = '1' then STATE_RW <= pol_state; pipeline_sel<= '0'; WALSH_OPREG_LOAD_INT<= '0'; FIBER_OPREG_LOAD_INT<= '0'; OPREG_LOAD <= '0'; SER_OPREG_LOAD_INT <= '0'; SCTN_OPREG_LOAD_INT<= '0'; RST_OPREG_LOAD_INT <= '0'; wr_en <= '0'; rd_en <= '0'; OPREG_WREN<= '0'; O_DATA_int1 <= (others => '0'); O_DATA_int2 <= (others => '0'); O_DATA_int3 <= (others => '0'); O_DATA_int4 <= (others => '0'); TO_USB <= (others => '0'); inc_loc_ctr <= '0'; inc_ch_ctr<= '0'; URAM_INC <= '0'; rst_uramloc_ctr <= '0'; URAM_RD_LD <= '0'; READ_complete <= '0'; URAM_RDEN <= '0'; OP_WR_EN1<= '0'; OP_WR_EN2<= '0'; rst_loc_ctr <= '1'; else case STATE_RW is when pol_state => wr_en <= '0'; rd_en <= '0'; inc_loc_ctr <= '0'; rst_loc_ctr <= '1'; WALSH_OPREG_LOAD_INT<= '0'; FIBER_OPREG_LOAD_INT<= '0'; OPREG_LOAD<= '0'; OP_WR_EN1 <= '0'; OP_WR_EN2 <= '0'; CHSEL_WREN_out_int<= '0'; inc_ch_ctr <= '0'; SER_OPREG_LOAD_INT<= '0'; SCTN_OPREG_LOAD_INT<= '0'; RST_OPREG_LOAD_INT<= '0'; if L_UADDR(1 DOWNTO 0) = CHIP_SEL and valid_WR = '1' then pipeline_sel<= '1'; POL_SELECTION_INT <= L_UADDR(2); if reg_addrs = "00000" then STATE_RW <= pol_state; --idle; elsif reg_addrs = "00001" then STATE_RW <= write1; --idle; --WALSH REG elsif reg_addrs = "00010" then STATE_RW <= write2; --idle; --GAIN RAM elsif reg_addrs = "00011" then STATE_RW <= write3; --idle; --CHSEL RAM elsif reg_addrs = "00100" then STATE_RW <= write4; --idle; --SERIALISER RAM elsif reg_addrs = "00101" then STATE_RW <= write5; --idle; --SCTN elsif reg_addrs = "00110" then STATE_RW <= write6; --idle; --SCTN elsif reg_addrs = "01000" then STATE_RW <= read1; --idle; elsif reg_addrs = "01101" then STATE_RW <= BURST_READ; --idle;-- pfb power read p2 else STATE_RW <= pol_state; --idle; end if; else pipeline_sel<= '0'; STATE_RW <= pol_state; --idle; end if; when write1 => --WALSH REGISTER WALSH_WREN_out <= wr_en; if go_back_w = '0' then wr_en <= '1'; if wr_en = '1' then if valid_WR = '1' then if U_WR_CNT = X"00" then O_DATA_int1<= TO_FPGA; CHECKSUM <= CHECKSUM xor TO_FPGA; elsif U_WR_CNT = X"01" then O_DATA_int2<= TO_FPGA; CHECKSUM <= CHECKSUM xor TO_FPGA; elsif U_WR_CNT = X"02" then O_DATA_int3<= TO_FPGA; CHECKSUM <= CHECKSUM xor TO_FPGA; elsif U_WR_CNT = X"03" then O_DATA_int4<= TO_FPGA; CHECKSUM <= CHECKSUM xor TO_FPGA; wr_en <= '0'; WALSH_OPREG_LOAD_INT <= '1'; else O_DATA_int1 <= O_DATA_int1; O_DATA_int2 <= O_DATA_int2; O_DATA_int3 <= O_DATA_int3; O_DATA_int4 <= O_DATA_int4; O_DATA_REG <= O_DATA_REG; wr_en <= wr_en; end if; else O_DATA_int1 <= O_DATA_int1; O_DATA_int2 <= O_DATA_int2; O_DATA_int3 <= O_DATA_int3; O_DATA_int4 <= O_DATA_int4; O_DATA_REG <= O_DATA_REG; wr_en <= wr_en; end if; end if; if WALSH_OPREG_LOAD_INT = '1' then CHECKSUM_OUT1 <= CHECKSUM; WALSH_OPREG_LOAD_INT<= '0'; STATE_RW <= pol_state; --idle; wr_en <= '0'; COMMAND1_DATA <= O_DATA_int4 & O_DATA_int3 & O_DATA_int2 & O_DATA_int1; end if; else STATE_RW <= pol_state; --idle; wr_en <= '0'; WALSH_OPREG_LOAD_INT<= '0'; end if; when write2 => --WALSH REGISTER FIBER_WREN_out <= wr_en; if go_back_w = '0' then wr_en <= '1'; if wr_en = '1' then if valid_WR = '1' then if U_WR_CNT = X"00" then O_DATA_int1<= TO_FPGA; CHECKSUM <= CHECKSUM xor TO_FPGA; elsif U_WR_CNT = X"01" then O_DATA_int2<= TO_FPGA; CHECKSUM <= CHECKSUM xor TO_FPGA; elsif U_WR_CNT = X"02" then O_DATA_int3<= TO_FPGA; CHECKSUM <= CHECKSUM xor TO_FPGA; elsif U_WR_CNT = X"03" then O_DATA_int4<= TO_FPGA; CHECKSUM <= CHECKSUM xor TO_FPGA; wr_en <= '0'; FIBER_OPREG_LOAD_INT <= '1'; else O_DATA_int1 <= O_DATA_int1; O_DATA_int2 <= O_DATA_int2; O_DATA_int3 <= O_DATA_int3; O_DATA_int4 <= O_DATA_int4; O_DATA_REG <= O_DATA_REG; wr_en <= wr_en; end if; else O_DATA_int1 <= O_DATA_int1; O_DATA_int2 <= O_DATA_int2; O_DATA_int3 <= O_DATA_int3; O_DATA_int4 <= O_DATA_int4; O_DATA_REG <= O_DATA_REG; wr_en <= wr_en; end if; end if; if FIBER_OPREG_LOAD_INT = '1' then CHECKSUM_OUT1 <= CHECKSUM; FIBER_OPREG_LOAD_INT<= '0'; STATE_RW <= pol_state; --idle; wr_en <= '0'; COMMAND2_DATA <= O_DATA_int4 & O_DATA_int3 & O_DATA_int2 & O_DATA_int1; end if; else STATE_RW <= pol_state; --idle; wr_en <= '0'; FIBER_OPREG_LOAD_INT<= '0'; end if; -- when write2 => --GAIN REGISTER -- if go_back_w = '0' then -- wr_en <= '1'; -- rst_loc_ctr <= '0'; -- if wr_en = '1' then -- if valid_WR = '1' then -- if U_WR_CNT = X"00" then -- O_DATA_int1<= TO_FPGA; -- elsif U_WR_CNT = X"01" then -- O_DATA_int2<= TO_FPGA; -- elsif U_WR_CNT = X"02" then -- O_DATA_int3<= TO_FPGA; -- elsif U_WR_CNT = X"03" then -- O_DATA_int4<= TO_FPGA; -- wr_en <= '0'; -- OPREG_LOAD <= '1'; -- inc_loc_ctr <= '1'; -- else -- O_DATA_int1 <= O_DATA_int1; -- O_DATA_int2 <= O_DATA_int2; -- O_DATA_int3 <= O_DATA_int3; -- O_DATA_int4 <= O_DATA_int4; -- O_DATA_REG <= O_DATA_REG; -- wr_en <= wr_en; -- OP_WR_EN1 <= OP_WR_EN1; -- OP_WR_EN2 <= OP_WR_EN2; -- end if; -- else -- O_DATA_int1 <= O_DATA_int1; -- O_DATA_int2 <= O_DATA_int2; -- O_DATA_int3 <= O_DATA_int3; -- O_DATA_int4 <= O_DATA_int4; -- O_DATA_REG <= O_DATA_REG; -- wr_en <= wr_en; -- OP_WR_EN1 <= OP_WR_EN1; -- OP_WR_EN2 <= OP_WR_EN2; -- end if; -- end if; -- if loc_ctr < 127 then -- OP_WR_EN1 <= '1'; -- OP_WR_EN2 <= '0'; -- elsif loc_ctr = 127 and OPREG_LOAD = '1' then --and L_UADDR(2) = '1' then -- OP_WR_EN1 <= '0'; -- OP_WR_EN2 <= '1'; -- elsif (loc_ctr > 127) and (loc_ctr < 255) then -- OP_WR_EN1 <= '0'; -- OP_WR_EN2 <= '1'; -- elsif loc_ctr = 255 and OPREG_LOAD = '1' then -- OP_WR_EN1 <= '0'; -- OP_WR_EN2 <= '0'; -- STATE_RW <= pol_state; --idle; -- wr_en <= '0'; -- inc_loc_ctr <= '0'; -- rst_loc_ctr <= '1'; -- OPREG_LOAD <= '0'; -- -- end if; -- if OPREG_LOAD = '1' then -- OPREG_LOAD <= '0'; -- wr_en <= wr_en; -- OP_WR_EN1 <= OP_WR_EN1; -- OP_WR_EN2 <= OP_WR_EN2; -- end if; -- if inc_loc_ctr = '1' then -- inc_loc_ctr <= '0'; -- end if; -- else -- STATE_RW <= pol_state; --idle; -- OP_WR_EN1 <= '0'; -- OP_WR_EN2 <= '0'; -- wr_en <= '0'; -- inc_loc_ctr <= '0'; -- rst_loc_ctr <= '1'; -- OPREG_LOAD <= '0'; -- -- end if; when write3 => --WALSH REGISTER WR_ENABLE <= wr_en; if go_back_w = '0' then wr_en <= '1'; if wr_en = '1' then if valid_WR = '1' then if U_WR_CNT = X"00" then O_DATA_int1<= TO_FPGA; CHECKSUM <= CHECKSUM xor TO_FPGA; elsif U_WR_CNT = X"01" then O_DATA_int2<= TO_FPGA; CHECKSUM <= CHECKSUM xor TO_FPGA; elsif U_WR_CNT = X"02" then O_DATA_int3<= TO_FPGA; CHECKSUM <= CHECKSUM xor TO_FPGA; elsif U_WR_CNT = X"03" then O_DATA_int4<= TO_FPGA; CHECKSUM <= CHECKSUM xor TO_FPGA; wr_en <= '0'; OPREG_LOAD <= '1'; else O_DATA_int1 <= O_DATA_int1; O_DATA_int2 <= O_DATA_int2; O_DATA_int3 <= O_DATA_int3; O_DATA_int4 <= O_DATA_int4; O_DATA_REG <= O_DATA_REG; wr_en <= wr_en; end if; else O_DATA_int1 <= O_DATA_int1; O_DATA_int2 <= O_DATA_int2; O_DATA_int3 <= O_DATA_int3; O_DATA_int4 <= O_DATA_int4; O_DATA_REG <= O_DATA_REG; wr_en <= wr_en; end if; end if; if OPREG_LOAD = '1' then CHECKSUM_OUT1 <= CHECKSUM; OPREG_LOAD<= '0'; STATE_RW <= pol_state; --idle; wr_en <= '0'; COMMAND3_DATA <= O_DATA_int4 & O_DATA_int3 & O_DATA_int2 & O_DATA_int1; end if; else STATE_RW <= pol_state; --idle; wr_en <= '0'; OPREG_LOAD<= '0'; end if; -- when write3 => --CHANNEL SELECTION REGISTER when write4 => --modifed for 9 locations delay modules values -- OPREG_WREN <= wr_en; if go_back_w = '0' then wr_en <= '1'; rst_loc_ctr <= '0'; -- CHSEL_WREN_out_int<= '1'; if wr_en = '1' then if valid_WR = '1' then if U_WR_CNT = X"00" then O_DATA_int1<= TO_FPGA; CHECKSUM <= CHECKSUM xor TO_FPGA; elsif U_WR_CNT = X"01" then O_DATA_int2<= TO_FPGA; CHECKSUM <= CHECKSUM xor TO_FPGA; elsif U_WR_CNT = X"02" then O_DATA_int3<= TO_FPGA; CHECKSUM <= CHECKSUM xor TO_FPGA; elsif U_WR_CNT = X"03" then O_DATA_int4<= TO_FPGA; CHECKSUM <= CHECKSUM xor TO_FPGA; wr_en <= '0'; OPREG_LOAD <= '1'; inc_ch_ctr <= '1'; -- if ch_ctr = 32 then -- ch_over <= '1'; -- CHSEL_WREN_out_int<= '0'; else O_DATA_int1 <= O_DATA_int1; O_DATA_int2 <= O_DATA_int2; O_DATA_int3 <= O_DATA_int3; O_DATA_int4 <= O_DATA_int4; O_DATA_REG <= O_DATA_REG; wr_en<= wr_en; end if; else O_DATA_int1 <= O_DATA_int1; O_DATA_int2 <= O_DATA_int2; O_DATA_int3 <= O_DATA_int3; O_DATA_int4 <= O_DATA_int4; O_DATA_REG <= O_DATA_REG; wr_en <= wr_en; end if; end if; if ch_ctr < 8 then CHSEL_WREN_out_int<= '1'; elsif ch_ctr = 8 and OPREG_LOAD = '1' then CHSEL_WREN_out_int<= '0'; CHECKSUM_OUT1 <= CHECKSUM; STATE_RW <= pol_state; --idle; wr_en <= '0'; inc_ch_ctr <= '0'; rst_loc_ctr <= '1'; OPREG_LOAD <= '0'; end if; if OPREG_LOAD = '1' then OPREG_LOAD <= '0'; wr_en <= wr_en; CHSEL_WREN_out_int<= CHSEL_WREN_out_int; COMMAND4_DATA <= O_DATA_int4 & O_DATA_int3 & O_DATA_int2 & O_DATA_int1; end if; if inc_ch_ctr = '1' then inc_ch_ctr <= '0'; end if; else STATE_RW <= pol_state; --idle; CHSEL_WREN_out_int<= '0'; wr_en<= '0'; inc_ch_ctr <= '0'; rst_loc_ctr <= '0'; OPREG_LOAD <= '0'; end if; -- when write4 => --SER ODDR REGISTER -- SER_WREN_out <= wr_en; -- if go_back_w = '0' then -- wr_en <= '1'; -- if wr_en = '1' then -- if valid_WR = '1' then -- if U_WR_CNT = X"00" then -- O_DATA_int1<= TO_FPGA; -- CHECKSUM <= CHECKSUM xor TO_FPGA; -- elsif U_WR_CNT = X"01" then -- O_DATA_int2<= TO_FPGA; -- CHECKSUM <= CHECKSUM xor TO_FPGA; -- elsif U_WR_CNT = X"02" then -- O_DATA_int3<= TO_FPGA; -- CHECKSUM <= CHECKSUM xor TO_FPGA; -- elsif U_WR_CNT = X"03" then -- O_DATA_int4<= TO_FPGA; -- CHECKSUM <= CHECKSUM xor TO_FPGA; -- wr_en <= '0'; -- SER_OPREG_LOAD_INT<= '1'; -- else -- O_DATA_int1 <= O_DATA_int1; -- O_DATA_int2 <= O_DATA_int2; -- O_DATA_int3 <= O_DATA_int3; -- O_DATA_int4 <= O_DATA_int4; -- O_DATA_REG <= O_DATA_REG; -- wr_en <= wr_en; -- end if; -- else -- O_DATA_int1 <= O_DATA_int1; -- O_DATA_int2 <= O_DATA_int2; -- O_DATA_int3 <= O_DATA_int3; -- O_DATA_int4 <= O_DATA_int4; -- O_DATA_REG <= O_DATA_REG; -- wr_en <= wr_en; -- end if; -- end if; -- if SER_OPREG_LOAD_INT = '1' then -- CHECKSUM_OUT1 <= CHECKSUM; -- SER_OPREG_LOAD_INT<= '0'; -- STATE_RW <= pol_state; --idle; -- wr_en <= '0'; -- end if; -- else -- STATE_RW <= pol_state; --idle; -- SER_OPREG_LOAD_INT<= '0'; -- wr_en <= '0'; -- end if; when write5 => --SCTN REGISTER SCTN_WREN_out <= wr_en; if go_back_w = '0' then wr_en <= '1'; if wr_en = '1' then if valid_WR = '1' then if U_WR_CNT = X"00" then O_DATA_int1<= TO_FPGA; CHECKSUM <= CHECKSUM xor TO_FPGA; elsif U_WR_CNT = X"01" then O_DATA_int2<= TO_FPGA; CHECKSUM <= CHECKSUM xor TO_FPGA; elsif U_WR_CNT = X"02" then O_DATA_int3<= TO_FPGA; CHECKSUM <= CHECKSUM xor TO_FPGA; elsif U_WR_CNT = X"03" then O_DATA_int4<= TO_FPGA; CHECKSUM <= CHECKSUM xor TO_FPGA; wr_en <= '0'; SCTN_OPREG_LOAD_INT <= '1'; else O_DATA_int1 <= O_DATA_int1; O_DATA_int2 <= O_DATA_int2; O_DATA_int3 <= O_DATA_int3; O_DATA_int4 <= O_DATA_int4; O_DATA_REG <= O_DATA_REG; wr_en <= wr_en; end if; else O_DATA_int1 <= O_DATA_int1; O_DATA_int2 <= O_DATA_int2; O_DATA_int3 <= O_DATA_int3; O_DATA_int4 <= O_DATA_int4; O_DATA_REG <= O_DATA_REG; wr_en <= wr_en; end if; end if; if SCTN_OPREG_LOAD_INT = '1' then CHECKSUM_OUT1 <= CHECKSUM; SCTN_OPREG_LOAD_INT<= '0'; STATE_RW <= pol_state; --idle; wr_en <= '0'; COMMAND5_DATA <= O_DATA_int4 & O_DATA_int3 & O_DATA_int2 & O_DATA_int1; end if; else STATE_RW <= pol_state; --idle; SCTN_OPREG_LOAD_INT<= '0'; wr_en <= '0'; end if; when write6 => --EXT_RST REGISTER EXTRST_WR_EN <= wr_en; if go_back_w = '0' then wr_en <= '1'; if wr_en = '1' then if valid_WR = '1' then if U_WR_CNT = X"00" then O_DATA_int1<= TO_FPGA; CHECKSUM <= CHECKSUM xor TO_FPGA; elsif U_WR_CNT = X"01" then O_DATA_int2<= TO_FPGA; CHECKSUM <= CHECKSUM xor TO_FPGA; elsif U_WR_CNT = X"02" then O_DATA_int3<= TO_FPGA; CHECKSUM <= CHECKSUM xor TO_FPGA; elsif U_WR_CNT = X"03" then O_DATA_int4<= TO_FPGA; CHECKSUM <= CHECKSUM xor TO_FPGA; wr_en <= '0'; RST_OPREG_LOAD_INT <= '1'; else O_DATA_int1 <= O_DATA_int1; O_DATA_int2 <= O_DATA_int2; O_DATA_int3 <= O_DATA_int3; O_DATA_int4 <= O_DATA_int4; O_DATA_REG <= O_DATA_REG; wr_en <= wr_en; end if; else O_DATA_int1 <= O_DATA_int1; O_DATA_int2 <= O_DATA_int2; O_DATA_int3 <= O_DATA_int3; O_DATA_int4 <= O_DATA_int4; O_DATA_REG <= O_DATA_REG; wr_en <= wr_en; end if; end if; if RST_OPREG_LOAD_INT = '1' then CHECKSUM_OUT1 <= CHECKSUM; RST_OPREG_LOAD_INT<= '0'; STATE_RW <= pol_state; --idle; wr_en <= '0'; COMMAND6_DATA <= O_DATA_int4 & O_DATA_int3 & O_DATA_int2 & O_DATA_int1; end if; else STATE_RW <= pol_state; --idle; RST_OPREG_LOAD_INT<= '0'; wr_en <= '0'; end if; when read1 => OPREG_RDEN <= rd_en; if go_back_w = '0' then rd_en <= '1'; if rd_en = '1' then if U_RD_CNT = X"00" then TO_USB<= CHECKSUM_OUT1; elsif U_RD_CNT = X"01" then TO_USB<= CHECKSUM_OUT1; elsif U_RD_CNT = X"02" then TO_USB<= CHECKSUM_OUT1; elsif U_RD_CNT = X"03" then TO_USB<= CHECKSUM_OUT1; elsif U_RD_CNT = X"04" then TO_USB<= TO_USB; rd_en <= '0'; STATE_RW <= pol_state; --idle; CHECKSUM_OUT1 <= (others => '0'); CHECKSUM <= (others => '0'); end if; end if; else STATE_RW <= pol_state; --idle; rd_en <= '0'; CHECKSUM_OUT1 <= (others => '0'); CHECKSUM <= (others => '0'); end if; when BURST_READ => Write_completel <= Write_complete; if Write_completel = '1' then -- or RW_DONE = '1' then READ_complete <= '0'; end if; -- OPREG_RDEN <= rd_en; if go_back_w = '0' then rd_en <= '1'; rst_uramloc_ctr <= '0'; -- if Write_completel = '1' then if rd_en = '1' then if U_RD_CNT = X"00" then URAM_RDEN <= '1'; -- rd_en <= '1'; -- TO_USB<= X"11"; --READ_status(7 DOWNTO 0); --O_DATA_int1; TO_USB<= READ_status(7 DOWNTO 0); --O_DATA_int1; elsif U_RD_CNT = X"01" then -- TO_USB<= X"22"; --READ_status(15 DOWNTO 8); --O_DATA_int2; TO_USB<= READ_status(15 DOWNTO 8); --O_DATA_int2; elsif U_RD_CNT = X"02" then -- TO_USB<= X"33"; --READ_status(23 DOWNTO 16);--O_DATA_int3; TO_USB<= READ_status(23 DOWNTO 16);--O_DATA_int3; elsif U_RD_CNT = X"03" then -- TO_USB<= X"44"; --READ_status(31 DOWNTO 24);--O_DATA_int4; TO_USB<= READ_status(31 DOWNTO 24);--O_DATA_int4; elsif U_RD_CNT = X"04" then TO_USB<= TO_USB; rd_en <= '0'; URAM_RD_LD <= '1'; URAM_INC <= '1'; rd_en <= '0'; -- STATE_RW <= pol_state; --idle; if uram_ctr = 31 then URAM_RDEN <= '0'; READ_complete <= '1'; end if; else TO_USB <= TO_USB; end if; -- end if; end if; if uram_ctr = 31 and URAM_RD_LD = '1' then rd_en <= '0'; rst_uramloc_ctr <= '1'; end if; if uram_ctr = 31 then CHECKSUM_OUT1 <= (others => '0'); CHECKSUM <= (others => '0'); end if; if URAM_RD_LD = '1' then URAM_RD_LD <= '0'; rd_en1 <= rd_en1; URAM_RDEN<= URAM_RDEN; end if; if URAM_INC = '1' then URAM_INC <= '0'; end if; if READ_complete = '1' then READ_complete <= '0'; end if; else STATE_RW <= pol_state; --idle; URAM_RDEN<= '0'; rd_en<= '0'; URAM_INC <= '0'; rst_uramloc_ctr <= '0'; URAM_RD_LD <= '0'; end if; --======================================================== end case; end if; END IF; end process; ------------------------------------------------------------------------------------------------- process(CLK) begin if CLK'event and CLK='1' then if RESET = '1' or rst_loc_ctr = '1' then loc_ctr <= (others => '0'); elsif inc_loc_ctr= '1' then loc_ctr <= loc_ctr + '1'; else loc_ctr <= loc_ctr; end if; end if; end process; ----------------------------------------------------------------- process(CLK) begin if CLK'event and CLK='1' then if RESET = '1' or rst_loc_ctr = '1' then ch_ctr <= (others => '0'); elsif inc_ch_ctr= '1' then ch_ctr <= ch_ctr + '1'; else ch_ctr <= ch_ctr; end if; end if; end process; --write counter process(valid_WR,RESET,wr_en,CLK) begin if CLK'event and CLK='1' then if OPREG_LOAD = '1' then U_WR_CNT <= (OTHERS => '0'); elsif wr_en = '0' and valid_WR = '0' then U_WR_CNT <= (OTHERS => '0'); elsif wr_en = '1' and valid_WR = '1' then U_WR_CNT <= U_WR_CNT + '1'; elsif wr_en = '1' and valid_WR = '0' then U_WR_CNT <= U_WR_CNT; else U_WR_CNT <= (OTHERS => '0'); end if; else U_WR_CNT <= U_WR_CNT; end if; end process; -- read counter process(valid_RD,RESET,rd_en,CLK) begin if CLK'event and CLK='1' then if rd_en = '0' then -- and valid_RD = '0' then U_RD_CNT <= (OTHERS => '0'); elsif rd_en = '1' and valid_RD = '1' then U_RD_CNT <= U_RD_CNT + '1'; elsif rd_en = '1' and valid_RD = '0' then U_RD_CNT <= U_RD_CNT; else U_RD_CNT <= (OTHERS => '0'); end if; else U_RD_CNT <= U_RD_CNT; end if; end process; ------------------------------------------------------------------------------------------------ --OUTPUT REGISTER PROCESS(CLK) BEGIN IF CLK'EVENT AND CLK = '1' THEN OUTPUT_REG(7 DOWNTO 0) <= O_DATA_int1; OUTPUT_REG(15 DOWNTO 8) <= O_DATA_int2; OUTPUT_REG(23 DOWNTO 16)<= O_DATA_int3; OUTPUT_REG(31 DOWNTO 24)<= O_DATA_int4; WALSH_OPREG_LOAD <= WALSH_OPREG_LOAD_INT; FIBER_OPREG_LOAD <= FIBER_OPREG_LOAD_INT; OPREG_LOAD_out <= OPREG_LOAD; GAIN_WREN1_OUT<= OP_WR_EN1; GAIN_WREN2_OUT<= OP_WR_EN2; CHSEL_WREN_out<= CHSEL_WREN_out_int; SER_OPREG_LOAD<=SER_OPREG_LOAD_INT; SCTN_OPREG_LOAD<=SCTN_OPREG_LOAD_INT; RST_OPREG_LOAD<= RST_OPREG_LOAD_INT; END IF; END PROCESS; PIPELINE_EN <= pipeline_sel; POL_SELECTION <= POL_SELECTION_INT; ----------------------------------------------------------------- process(CLK) begin if CLK'event and CLK='1' then if RESET = '1' or rst_uramloc_ctr = '1' then uram_ctr <= (others => '0'); elsif URAM_INC= '1' then --and valid_RD = '1' then uram_ctr <= uram_ctr + '1'; else uram_ctr <= uram_ctr; end if; end if; end process; process(CLK2) begin if(CLK2'event and CLK2 = '1') then SCTN_L <= SCTN; READ_completel<=READ_complete; if SCTN_L = '0' then CHECKSUM_OUT2 <= CHECKSUM_OUT1; end if; if SCTN_L = '0' and poll_next_sctn = '0' then wr_addrs <= (others => '0'); poll_next_sctn <= '1'; USB_READRAM_IP <= X"000000" & CHECKSUM_OUT2; WE_EN <= '1'; elsif SCTN_L = '1' and poll_next_sctn = '1' and Write_complete = '0' then wr_addrs <= wr_addrs + '1'; if wr_addrs = 0 then USB_READRAM_IP <= X"ACFC1234"; elsif wr_addrs = 1 then USB_READRAM_IP <= CLKCOUNT; --X"e9e9e9e9"; --TO_USB_READ1; elsif wr_addrs = 2 then USB_READRAM_IP <= SCTNCOUNT; --X"e9e9e9e9"; --TO_USB_READ1; elsif wr_addrs = 3 then USB_READRAM_IP <= COMMAND1_DATA; --X"e9e9e9e9"; --TO_USB_READ1; elsif wr_addrs = 4 then USB_READRAM_IP <= COMMAND2_DATA; --X"e9e9e9e9"; --TO_USB_READ1; elsif wr_addrs = 5 then USB_READRAM_IP <= COMMAND3_DATA; --X"e9e9e9e9"; --TO_USB_READ1; elsif wr_addrs = 6 then USB_READRAM_IP <= COMMAND4_DATA; --X"e9e9e9e9"; --TO_USB_READ1; elsif wr_addrs = 7 then USB_READRAM_IP <= COMMAND5_DATA; --X"e9e9e9e9"; --TO_USB_READ1; elsif wr_addrs = 8 then USB_READRAM_IP <= COMMAND6_DATA; --X"e9e9e9e9"; --TO_USB_READ1; elsif wr_addrs = 9 then USB_READRAM_IP <= X"ACFC1234"; --X"e9e9e9e9"; --TO_USB_READ1; elsif wr_addrs = 10 then USB_READRAM_IP <= TO_USB_READ1; --X"e9e9e9e9"; --TO_USB_READ1; elsif wr_addrs = 11 then USB_READRAM_IP <= TO_USB_READ2; --X"d8d8d8d8"; --TO_USB_READ2; elsif wr_addrs = 12 then USB_READRAM_IP <= TO_USB_READ3; --X"c7c7c7c7"; --TO_USB_READ3; elsif wr_addrs = 13 then USB_READRAM_IP <= TO_USB_READ4; --X"b6b6b6b6"; -- TO_USB_READ4; elsif wr_addrs = 14 then USB_READRAM_IP <= TO_USB_READ5; --X"a5a5a5a5" ; --TO_USB_READ5; elsif wr_addrs = 15 then USB_READRAM_IP <= tile0refclk1_cnt; --X"a5a5a5a5" ; --TO_USB_READ5; elsif wr_addrs = 16 then USB_READRAM_IP <= tile1refclk1_cnt; --X"a5a5a5a5" ; --TO_USB_READ5; elsif wr_addrs = 17 then USB_READRAM_IP <= tile0txclk_cnt; --X"a5a5a5a5" ; --TO_USB_READ5; elsif wr_addrs = 18 then USB_READRAM_IP <= tile1txclk_cnt; --X"a5a5a5a5" ; --TO_USB_READ5; elsif wr_addrs = 19 then USB_READRAM_IP <= tile0rxclk0_cnt; --X"a5a5a5a5" ; --TO_USB_READ5; elsif wr_addrs = 20 then USB_READRAM_IP <= tile0rxclk1_cnt; --X"a5a5a5a5" ; --TO_USB_READ5; elsif wr_addrs = 21 then USB_READRAM_IP <= tile1rxclk0_cnt; --X"a5a5a5a5" ; --TO_USB_READ5; elsif wr_addrs = 22 then USB_READRAM_IP <= tile1rxclk1_cnt; --X"a5a5a5a5" ; --TO_USB_READ5; elsif wr_Addrs > 22 and wr_addrs <= 30 then USB_READRAM_IP <= X"01234567"; elsif wr_addrs = 31 then Write_complete <= '1'; WE_EN <= '0'; USB_READRAM_IP <= (others => '0'); end if; END IF; if READ_completel = '1' then Write_complete <= '0'; poll_next_sctn <= '0'; -- RW_DONE <= '1'; end if; if SCTN_L = '0' then CLKCOUNT <= (Others => '0'); SCTNCOUNT <= SCTNCOUNT + '1'; else CLKCOUNT <= CLKCOUNT + '1'; end if; end if; -------------------------------------------------------------- end process; --process(tile0_refclkout_i_out) --begin -- if tile0_refclkout_i_out'event and tile0_refclkout_i_out = '1' then -- if mgtreset = '1' then -- tile0refclk1_cnt <= (others => '0'); -- else -- tile0refclk1_cnt <= tile0refclk1_cnt + '1'; -- end if; -- end if; --end process; -- --process(tile1_refclkout_i_out) --begin -- if tile1_refclkout_i_out'event and tile1_refclkout_i_out = '1' then -- if mgtreset = '1' then -- tile1refclk1_cnt <= (others => '0'); -- else -- tile1refclk1_cnt <= tile1refclk1_cnt + '1'; -- end if; -- end if; --end process; process(TILE0_TXUSRCLK20_OUT) begin if TILE0_TXUSRCLK20_OUT'event and TILE0_TXUSRCLK20_OUT = '1' then if mgtreset = '1' then tile0txclk_cnt <= (others => '0'); else tile0txclk_cnt <= tile1txclk_cnt + '1'; end if; end if; end process; process(TILE1_TXUSRCLK20_OUT) begin if TILE1_TXUSRCLK20_OUT'event and TILE1_TXUSRCLK20_OUT = '1' then if mgtreset = '1' then tile1txclk_cnt <= (others => '0'); else tile1txclk_cnt <= tile1txclk_cnt + '1'; end if; end if; end process; process(tile0_rxclk0_i) begin if tile0_rxclk0_i'event and tile0_rxclk0_i = '1' then if mgtreset = '1' then tile0rxclk0_cnt <= (others => '0'); else tile0rxclk0_cnt <= tile0rxclk0_cnt + '1'; end if; end if; end process; process(tile0_rxclk1_i) begin if tile0_rxclk1_i'event and tile0_rxclk1_i = '1' then if mgtreset = '1' then tile0rxclk1_cnt <= (others => '0'); else tile0rxclk1_cnt <= tile0rxclk1_cnt + '1'; end if; end if; end process; process(tile1_rxclk0_i) begin if tile1_rxclk0_i'event and tile1_rxclk0_i = '1' then if mgtreset = '1' then tile1rxclk0_cnt <= (others => '0'); else tile1rxclk0_cnt <= tile1rxclk0_cnt + '1'; end if; end if; end process; process(tile1_rxclk1_i) begin if tile1_rxclk1_i'event and tile1_rxclk1_i = '1' then if mgtreset = '1' then tile1rxclk1_cnt <= (others => '0'); else tile1rxclk1_cnt <= tile1rxclk1_cnt + '1'; end if; end if; end process; dp1 : usbreadram32 port map ( clka => CLK2, dina => USB_READRAM_IP, addra => wr_addrs, ena => WE_EN, wea => wea, clkb => CLK, addrb => uram_ctr, --rd_addrs, enb => URAM_RDEN, --rd_enram1, doutb => READ_status ); --READ_REG1 <= TO_USB_RE wea <= (others => '1'); End Behavioral; --------- end of file : usb_agof1.vhd ---------------------------