----------------------------------------------------------------
-- Project : agfo10_a.ise -- 25042008-RRI-RAL-hydrus-KPA
-- File    : usb_command1.vhd 
----------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL; 
library UNISIM;
use UNISIM.VComponents.all;
use IEEE.numeric_std.all;

entity usb_command_fiber is
    Port (  
    RST_USB          	: in std_logic;	 
	 clk_in 		       	: in std_logic;
 	 usb_data_in   	 	: in std_logic_vector(31 downto 0);
	 usb_load1 	 			: in std_logic;
	 usb_load2   	 		: in std_logic;
	 
	 
	 FIBRE_BKPLN_SEL		: out std_logic;
	 ch_sel_reg_out		: out std_logic_vector(7 downto 0);
	 VSIB_FIBRE_NUM		: out std_logic_vector(1 downto 0);

	 fibre_no_out		 	: out STD_LOGIC_VECTOR(2 downto 0);
    no_ch_fibre1_out  	: out STD_LOGIC_VECTOR(2 downto 0);   --0 to 7 chs
	 no_ch_fibre2_out 	: out STD_LOGIC_VECTOR(2 downto 0);   --8 to 15 chs
	 no_ch_fibre3_out 	: out STD_LOGIC_VECTOR(2 downto 0);  --16 to 23 chs
	 no_ch_fibre4_out 	: out STD_LOGIC_VECTOR(2 downto 0); --24 to 31 chs			  
	 actual_diag			: out std_logic;
	 node						: out STD_LOGIC_VECTOR(7 downto 0)
	 
   );
end usb_command_fiber;
-----------------------------------------------------------------
architecture Behavioral of usb_command_fiber is

signal usbL1,usbL : std_logic_vector(31 downto 0);
signal check_ld_low,usb_load_int,valid_load,lreset : std_logic;
signal check_ld_low1,usb_load_int1,valid_load1 : std_logic;


-----------------------------------------------------------------
begin

-----------------------------------------------------------------
process(clk_in)
begin
  if clk_in'event and clk_in = '1' then 
--   if(reset = '1') then
	if lreset = '1' then
	  check_ld_low <= '0';
	end if;  	
   usb_load_int <= usb_load1;
  	if usb_load_int = '1' and check_ld_low = '0' then
		  valid_load <= '1';
		  check_ld_low <= '1';
	elsif usb_load_int = '1' and check_ld_low = '1' then 	  
		  valid_load <= valid_load ;
		  check_ld_low <= check_ld_low;
	elsif usb_load_int = '0' and check_ld_low = '1' then
		  check_ld_low<= '0';
		  valid_load <= valid_load;
	elsif usb_load_int = '0' and check_ld_low = '0' then		
		  valid_load <= valid_load ;
		  check_ld_low<= '0';--check_ld_low;
	end if;	  
   if valid_load = '1' then
	    valid_load <= '0';
       usbL <= usb_data_in;
   end if;	

	ch_sel_reg_out <= usbL(7 downto 0);	
   FIBRE_BKPLN_SEL <= usbL(8); 		
	VSIB_FIBRE_NUM	 <= usbL(10 downto 9);	
	
  end if;
end process;

process(clk_in)
begin
  if clk_in'event and clk_in = '1' then 
     lreset <= RST_USB; --rst;
   if(lreset = '1') then
	  check_ld_low1 <= '0';
	else
     usb_load_int1 <= usb_load2;
  	   if usb_load_int1 = '1' and check_ld_low1 = '0' then
		   valid_load1 <= '1';
		   check_ld_low1 <= '1';
	   elsif usb_load_int1 = '1' and check_ld_low1 = '1' then 	  
		   valid_load1 <= valid_load1 ;
		   check_ld_low1 <= check_ld_low1;
	   elsif usb_load_int1 = '0' and check_ld_low1 = '1' then
		     check_ld_low1<= '0';
		     valid_load1 <= valid_load1;
	   elsif usb_load_int1 = '0' and check_ld_low1 = '0' then		
		     valid_load1 <= valid_load1 ;
		  check_ld_low1<= '0';--check_ld_low;
    	end if;	  
      if valid_load1 = '1' then
	    valid_load1 <= '0';
       usbL1 <= usb_data_in;
      end if;	
	 end if;	
--to write_en_gen	 

 	 fibre_no_out <= usbL1(2 downto 0);
    no_ch_fibre1_out <= usbL1(5 downto 3);   --0 to 7 chs
    no_ch_fibre2_out <= usbL1(8 downto 6);   --8 to 15 chs
    no_ch_fibre3_out <= usbL1(11 downto 9);  --16 to 23 chs
    no_ch_fibre4_out <= usbL1(14 downto 12); --24 to 31 chs
	 actual_diag <= usbL1(15); -- actual data or counter data sel 
    node <= usbL1(23 downto 16);

  end if;
end process;



End Behavioral;
--------------- end of file : usb_command1.vhd ------------------