---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 12:44:30 07/19/2008 -- Design Name: -- Module Name: write_en_gen - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; --use IEEE.STD_LOGIC_SIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. library UNISIM; use UNISIM.VComponents.all; entity write_en_gen is Port ( clk_165 : in STD_LOGIC; --165Mhz clk data_load : in STD_LOGIC; -- latched Valid_receb valid_enable : in STD_LOGIC; -- latched valid enable rst : in STD_LOGIC; fibre_no : in STD_LOGIC_VECTOR(2 downto 0); no_ch_fibre1 : in STD_LOGIC_VECTOR(5 downto 3); no_ch_fibre2 : in STD_LOGIC_VECTOR(8 downto 6); no_ch_fibre3 : in STD_LOGIC_VECTOR(11 downto 9); no_ch_fibre4 : in STD_LOGIC_VECTOR(14 downto 12); rd_complete : in STD_LOGIC; --outputs addra : out STD_LOGIC_VECTOR(2 downto 0); wr_en1 : out STD_LOGIC_VECTOR(0 downto 0); wr_en2 : out STD_LOGIC_VECTOR(0 downto 0); wr_en3 : out STD_LOGIC_VECTOR(0 downto 0); wr_en4 : out STD_LOGIC_VECTOR(0 downto 0); start_rd1 : out STD_LOGIC; start_rd2 : out STD_LOGIC; start_rd3 : out STD_LOGIC; start_rd4 : out STD_LOGIC ); end write_en_gen; architecture Behavioral of write_en_gen is signal addra_int,addra_int1 : std_logic_vector(2 downto 0); signal no_ch_fibre_cnt, fibre_no_cnt : std_logic_vector(2 downto 0); signal usbL1 : std_logic_vector(31 downto 0); signal lreset, wr_complete1, wr_complete2, wr_complete3, wr_complete4,wr_en1_int,wr_en2_int,wr_en3_int,wr_en4_int : std_logic; signal start_rd_flg : std_logic; BEGIN process(clk_165) begin if clk_165'event and clk_165 = '1' then lreset <= rst; if lreset = '1' then addra_int <=(others => '0'); no_ch_fibre_cnt <=(others => '0'); fibre_no_cnt <= "001"; start_rd_flg <= '0'; wr_en1(0) <= '0'; wr_en2(0) <= '0'; wr_en3(0) <= '0'; wr_en4(0) <= '0'; wr_en1_int <= '0'; wr_en2_int <= '0'; wr_en3_int <= '0'; wr_en4_int <= '0'; start_rd1 <= '0'; start_rd2 <= '0'; start_rd3 <= '0'; start_rd4 <= '0'; wr_complete1 <= '0'; wr_complete2 <= '0'; wr_complete3 <= '0'; wr_complete4 <= '0'; -- else -- elsif fibre_no > 0 then -- elsif (fibre_no > 0 and rd_complete = '0') then -- anish April 1, 2009 elsif (fibre_no > 0 and valid_enable = '1') then start_rd_flg <= '0'; -- wr_en1(0) <= '1'; ------------FIBRE -1 --------------------------------------------------------------- if fibre_no_cnt = "001" and no_ch_fibre_cnt <= no_ch_fibre1 and wr_complete1 = '0' then -- if fibre_no_cnt = "001" and no_ch_fibre_cnt <= 7 and wr_complete1 = '0' then wr_en2(0) <= '0'; wr_en3(0) <= '0'; wr_en4(0) <= '0'; wr_en2_int <= '0'; wr_en3_int <= '0'; wr_en4_int <= '0'; if data_load = '1' and no_ch_fibre_cnt < no_ch_fibre1 then -- if data_load = '1' and no_ch_fibre_cnt < 7 then wr_en1(0) <= '1'; wr_en1_int <= '1'; no_ch_fibre_cnt <= no_ch_fibre_cnt + '1'; start_rd1 <= '1'; addra_int <= addra_int + '1'; elsif data_load = '1' and no_ch_fibre_cnt = no_ch_fibre1 and fibre_no_cnt < fibre_no then -- elsif data_load = '1' and no_ch_fibre_cnt = 7 and fibre_no_cnt < 1 then wr_en1(0) <= '1'; wr_en1_int <= '1'; no_ch_fibre_cnt <= (others => '0'); start_rd1 <= '1'; addra_int <=(others => '0'); fibre_no_cnt <= fibre_no_cnt + '1'; wr_complete1 <= '1'; elsif data_load = '1' and no_ch_fibre_cnt = no_ch_fibre1 and fibre_no_cnt = fibre_no then -- elsif data_load = '1' and no_ch_fibre_cnt = 7 and fibre_no_cnt = 1 then wr_en1(0) <= '1'; wr_en1_int <= '1'; no_ch_fibre_cnt <= (others => '0'); start_rd1 <= '1'; addra_int <=(others => '0'); fibre_no_cnt <= "001"; wr_complete1 <= '1'; else wr_en1(0) <= '0'; wr_en1_int <= '0'; end if; ------------FIBRE -2 --------------------------------------------------------------- elsif fibre_no_cnt = "010" and no_ch_fibre_cnt <= no_ch_fibre2 and wr_complete2 = '0' then wr_en1(0) <= '0'; wr_en3(0) <= '0'; wr_en4(0) <= '0'; wr_en1_int <= '0'; wr_en3_int <= '0'; wr_en4_int <= '0'; if data_load = '1' and no_ch_fibre_cnt < no_ch_fibre2 then wr_en2(0) <= '1'; wr_en2_int <= '1'; no_ch_fibre_cnt <= no_ch_fibre_cnt + '1'; start_rd2 <= '1'; addra_int <= addra_int + '1'; elsif data_load = '1' and no_ch_fibre_cnt = no_ch_fibre2 and fibre_no_cnt < fibre_no then wr_en2(0) <= '1'; wr_en2_int <= '1'; no_ch_fibre_cnt <= (others => '0'); start_rd2 <= '1'; addra_int <=(others => '0'); fibre_no_cnt <= fibre_no_cnt + '1'; wr_complete2 <= '1'; elsif data_load = '1' and no_ch_fibre_cnt = no_ch_fibre2 and fibre_no_cnt = fibre_no then wr_en2(0) <= '1'; wr_en2_int <= '1'; no_ch_fibre_cnt <= (others => '0'); start_rd2 <= '1'; addra_int <=(others => '0'); fibre_no_cnt <= "001"; wr_complete2 <= '1'; else wr_en2(0) <= '0'; wr_en2_int <= '0'; end if; --------------FIBRE -3 --------------------------------------------------------------- elsif fibre_no_cnt = "011" and no_ch_fibre_cnt <= no_ch_fibre3 and wr_complete3 = '0' then wr_en1(0) <= '0'; wr_en2(0) <= '0'; wr_en4(0) <= '0'; wr_en1_int <= '0'; wr_en2_int <= '0'; wr_en4_int <= '0'; if data_load = '1' and no_ch_fibre_cnt < no_ch_fibre3 then wr_en3(0) <= '1'; wr_en3_int <= '1'; no_ch_fibre_cnt <= no_ch_fibre_cnt + '1'; start_rd3 <= '1'; addra_int <= addra_int + '1'; elsif data_load = '1' and no_ch_fibre_cnt = no_ch_fibre3 and fibre_no_cnt < fibre_no then wr_en3(0) <= '1'; wr_en3_int <= '1'; no_ch_fibre_cnt <= (others => '0'); start_rd3 <= '1'; addra_int <=(others => '0'); fibre_no_cnt <= fibre_no_cnt + '1'; wr_complete3 <= '1'; elsif data_load = '1' and no_ch_fibre_cnt = no_ch_fibre3 and fibre_no_cnt = fibre_no then wr_en3(0) <= '1'; wr_en3_int <= '1'; no_ch_fibre_cnt <= (others => '0'); start_rd3 <= '1'; addra_int <=(others => '0'); fibre_no_cnt <= "001"; wr_complete3 <= '1'; else wr_en3(0) <= '0'; wr_en3_int <= '0'; end if; --------------FIBRE -4 --------------------------------------------------------------- elsif fibre_no_cnt = "100" and no_ch_fibre_cnt <= no_ch_fibre4 and wr_complete4 = '0' then wr_en1(0) <= '0'; wr_en2(0) <= '0'; wr_en3(0) <= '0'; wr_en1_int <= '0'; wr_en2_int <= '0'; wr_en3_int <= '0'; if data_load = '1' and no_ch_fibre_cnt < no_ch_fibre4 then wr_en4(0) <= '1'; wr_en4_int <= '1'; no_ch_fibre_cnt <= no_ch_fibre_cnt + '1'; start_rd4 <= '1'; addra_int <= addra_int + '1'; elsif data_load = '1' and no_ch_fibre_cnt = no_ch_fibre4 and fibre_no_cnt < fibre_no then wr_en4(0) <= '1'; wr_en4_int <= '1'; no_ch_fibre_cnt <= (others => '0'); start_rd4 <= '1'; addra_int <=(others => '0'); fibre_no_cnt <= fibre_no_cnt + '1'; wr_complete4 <= '1'; elsif data_load = '1' and no_ch_fibre_cnt = no_ch_fibre4 and fibre_no_cnt = fibre_no then wr_en4(0) <= '1'; wr_en4_int <= '1'; no_ch_fibre_cnt <= (others => '0'); start_rd4 <= '1'; addra_int <=(others => '0'); fibre_no_cnt <= "001"; wr_complete4 <= '1'; else wr_en4(0) <= '0'; wr_en4_int <= '0'; end if; elsif wr_complete1 = '1' and wr_en1_int = '1' then wr_en1(0) <= '0'; wr_en1_int <= '0'; elsif wr_complete2 = '1' and wr_en2_int = '1' then wr_en2(0) <= '0'; wr_en2_int <= '0'; elsif wr_complete3 = '1' and wr_en3_int = '1' then wr_en3(0) <= '0'; wr_en3_int <= '0'; elsif wr_complete4 = '1' and wr_en4_int = '1' then wr_en4(0) <= '0'; wr_en4_int <= '0'; end if; ------------------------------------------------ -- elsif (fibre_no > 0 and rd_complete = '1') then --anish April 1, 2009 elsif (fibre_no > 0 and valid_enable = '0' and start_rd_flg = '0') then -- if(rd_complete = '1') then addra_int <=(others => '0'); no_ch_fibre_cnt <=(others => '0'); fibre_no_cnt <= "001"; wr_complete1 <= '0'; wr_complete2 <= '0'; wr_complete3 <= '0'; wr_complete4 <= '0'; wr_en1(0) <= '0'; wr_en2(0) <= '0'; wr_en3(0) <= '0'; wr_en4(0) <= '0'; wr_en1_int <= '0'; wr_en2_int <= '0'; wr_en3_int <= '0'; wr_en4_int <= '0'; start_rd_flg <= '1'; -- start_rd1 <= '0'; -- start_rd2 <= '0'; -- start_rd3 <= '0'; -- start_rd4 <= '0'; -- end if; elsif (fibre_no > 0 and valid_enable = '0' and start_rd_flg = '1') then start_rd1 <= '0'; start_rd2 <= '0'; start_rd3 <= '0'; start_rd4 <= '0'; end if; end if; end process; --pipeline delay adjust process(clk_165) begin if clk_165'event and clk_165 ='1' then --addra_int1 <= addra_int; --addra <= addra_int1; addra <= addra_int; end if; end process; END Behavioral;